Paper Code: ETEC-308	L          T          C
Paper: VLSI DESIGN	3           1           4

UNIT - I

Evolution of VLSI, MOS transistor theory – MOS structure, enhancement & depletion transistor, Threshold voltage, MOS device design equations,
CMOS inverter- DC characteristics, static load MOS inverter, pull up/pull down ratio, state & Dynamic power dissipation, CMOS & NMOS process technology – explanation of different stages in fabrication, latch up.

UNIT - II

Switching characteristics & inter connection effects:

Rise time, fall time delays Inverter design with delay constants. Parasitic effect, Super buffer.
CMOS logic gate design: Fan in, fan out Typical NAND, NOR, delays Transistor Sizing XOR, and XNOR gates.
CMOS logic structures: CMOS complimentary logic, Pseduo NMOS logic

UNIT - III

Clocked CMOS logic , pass transistor logic , domino , zipper CMOS.

Clocking strategies:

Clocked system, latches & Registers, system timing set-up & hold timing, signal phase memory structure, 2 phase clocking, Two phase memory structure

UNIT - IV

Two phase logic structure; four phase memory & logic structure
VLSI designing methodology – Introduction, VLSI designs flow, Design Hierarchy Concept of regularity, Modularity & Locality, VLSI design style, Design quality. Computer aided design technology: Design capture and verification tools.

TEXT BOOKS:

1. S. M. Kang, Y. Lebiebici, “CMOS digital integrated circuits analysis & design” TMH, 3rd Edition.
2. Weste and Eshrighian, “Principle of CMOS VLSI Design”  Pearson Education, 2001.

REFERENCE BOOKS:

1. R. J. Baker, H.W.Li, D. E. Boyce, “CMOS Circuit Design, Layout and Simulation” PHI – 2000.
2. J. M. Rabaey, “Digital Integrated Circuits” PHI – 2nd Edition.
3. W. Wolf Pearson, “Modern VLSI Design Systems on Silicon” Pearson Education – 2nd Edition.
4. J. P. Vyenmura, “Introduction to VLSI Circuits and Systems” John Wiely, 1st Edition.